An Implementation of High Performance IIR Filtration on 2-MAC Blackfin DSP Architecture
نویسنده
چکیده
The paper presents a new optimized implementation of IIR biquad filtration routine for highperformance 16-bit fixed point Blackfin DSPs. The core of hand-optimized routine uses both MAC units available in Blackfin architectures and in contrary to other available solutions it does not produce pipeline stalls in the DSP control and MAC units. The proposed core is the fastest currently available IIR biquad code for Blackfin ADSP-BF535 DSP. The core reaches asymptotically a theoretical minimum of 2.5 cycles per biquad and provides features that are not currently available in VisualDSP++ supporting DSP library functions. The functionality of the proposed implementation was fully tested in VisualDSP++ simulator and evaluated with ADSP-BF535EZ-Kit hardware. Index terms – IIR, biquad, library function, VisualDSP++, pipeline stalls
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